| 摘要 |
PURPOSE:To obtain a frame synchronizing circuit with high stability by inputting respectively each dissidence detecting ouput of two patterns in the complementary relation to an OR circuit and an AND circuit to select any output of both the logical circuits. CONSTITUTION:F and F' paterns being in the complementary relation are inputted respectively to pattern detecting circuits DET1 and DET2 and when the dissidence of each pattern is detected, a detected output is inputted to an OR circuit and an AND circuit. When a frame synchronization pattern generating circuit FRAME detects out-of-synchronism, a selector SEL connects the output of the OR circuit to a protection circuit PROTECT to prevent psudo out-of-synchronism thereby allowing quick synchronism locking. When the circuit is in the synchronizing state, the SEL connects the output of the AND circuit to the PROTECT, resulting in that the discrimination of out of synchronism due to code error is avoided and stable synchronizing state is kept. |
