发明名称 |
EXTERNAL SYNCHRONIZING CIRCUIT |
摘要 |
PURPOSE:To use a dynamic memory as a display memory by synchronizing horizontally and vertically synchronizing signals obtained from the external through a television with display system timing generated in its inside without amplifying jitter. CONSTITUTION:A source oscillation clock 1 has an almost fixed phase relation to an external horizontally synchronizing signal 10 and an external vertically synchronizing signal 11. A clock generating circuit 2 generates a clock stop timing signal 13 showing timing generating no trouble even if a column address entering signal of a dynamic RAM, a row address entering signal and a one-picture element clock are interrupted to control the stop of the clock. A horizontal counter 3 counts up the number of picture elements in the horizontal direction, converts the counted value 6 and generates a horizontal system displaying address. A vertical counter 5 generates a vertical system display address 9. A vertical synchronization forecasting circuit 7 determines a timing enabled to stop a clock immediately before the succeeding horizontal synchronization position from the timing receiving the external horizontally synchronizing signal 10.
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申请公布号 |
JPS60213181(A) |
申请公布日期 |
1985.10.25 |
申请号 |
JP19840067664 |
申请日期 |
1984.04.06 |
申请人 |
HITACHI SEISAKUSHO KK |
发明人 |
KOMATSU SHIGERU;OKAMOTO SADAJI;TAKAHARA YASUAKI |
分类号 |
G09G1/00;G09G1/04;G09G5/12;G09G5/18;H04N5/445;H04N7/025;H04N7/03;H04N7/035;H04N7/08;H04N7/081 |
主分类号 |
G09G1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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