| 摘要 |
PURPOSE:To reduce the erroneous detection of a synchronizing signal by constituting the synchronizing signal so as to be a pulse string of 50% duty, and during the receiving period of data obtained after the detection of the synchronizing signal, locking the operation of frequency dividing circuit. CONSTITUTION:The rise of a transmission signal TDT is detected by a detecting circuit 4 and its detecting signal TDTE is inputted to the reset input RS of the frequency dividing circuit 5 through an AND gate 9 to reset the signal TDTE. After resetting the signal TDTE, the circuit 5 counts up a clock CLK from a clock generator 6 and outputs a data clock signal SCLK frequency- divided into 1/4. An AND gate 7 passes the transmission signal TDT on the basis of the signal SCLK and stores the TDT in a shift register 8. Since a signal RDT from the register 8 is inputted to a detecting circuit 10, a synchronizing signal SYND is turned to ''0'' when the contents of the signal RDT goes to ''11001100'' to detect the synchronization, so that the AND gate 9 is closed, the synchronization of the circuit 5 with the transmission signal TDT is held and the signal TDT is correctly inputted to the shift register 8. |
