发明名称 |
DYNAMIC RAM |
摘要 |
PURPOSE:To speed up operation with simple constitution by matching the precharge end timing of a data line with word line selecting timing almost simultaneously. CONSTITUTION:When the word line selecting timing signal phiX is raised to its H level almost simultaneously with the decay timing t1 of the L level of a precharge pulse phiPCM, one word line W determined by complementary address signals aO-aB supplied through a multiplexer MPX synchronously with said rise is raised to the H level and turned to the selected status. Consequently, plural memory cells coupled with the selected word line are selected and the information storing MOS capacity of each memory cell is coupled with a data line D (or -D) through an address selecting MOSFET. |
申请公布号 |
JPS60212895(A) |
申请公布日期 |
1985.10.25 |
申请号 |
JP19840067757 |
申请日期 |
1984.04.06 |
申请人 |
HITACHI MAIKURO COMPUTER ENGINEERING KK;HITACHI SEISAKUSHO KK |
发明人 |
OBARA TAKAHIRO;OOISHI KANJI |
分类号 |
G11C11/407;G11C11/34;G11C11/403;G11C11/408;G11C11/409;(IPC1-7):G11C11/34 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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