| 摘要 |
PURPOSE:To obtain a descrambling circuit of a low power consumption and a high operation speed and to reduce the monopolized area by constituting the descrambling circuit with a counter, which is counted up by input of a clock signal, and an adder which adds the output signal of the counter. CONSTITUTION:The descrambling circuit consists of a counter 1, which is counted up by input of a clock signal CK, and an adder 3 which adds the output signal of the counter 1. Signals counted up by the clock are outputted to output terminals QA-QE of the counter 1. These output signals are inputted to input terminals A0-A2, A4, B1, and B2 of the adder 3, and the addition result is outputted as output signals SIGMA0-SIGMA4 from output terminals O0-O4. Input signals to the other input terminals A3, B0, B3, and B4 are logical ''0''. Thus, the descrambling circuit of a smaller monopolized area is obtained. |
