发明名称 SIGMA ARITHMETIC CIRCUIT OF REED SOLOMON CODING AND DECODING SYSTEM
摘要 PURPOSE:To obtain coefficients sigma1, sigma2 of an error position polynomial with simple circuit constitution by inputting properly syndromes S0-S3 from a common bus in matching with each operating processing, storing the product sum of the syndromes to a latch section, applying the operation of the coefficients sigma1, sigma2 of the error position polynomial again via the common bus and outputting the result as a vector. CONSTITUTION:Each syndrome is inputted to a vector/exponential converting section 2 from the common bus 1 and multiplication/division of the syndromes is applied by adding/subtracting a power exponent at an MOD operating section 6. The output of the MOD arithmetic section 6 is converted into a vector by at an exponent/vector converting section 11 again, the product sum of the syndromes corresponding to each term of the numerator/denominator of the coefficients sigma1, sigma2 is applied at a vector adder section of the next stage and the result is stored in a product sum latch section 20. The result S1<2>+S0S2, S0S3+S1S2, S2<2>+S1S3 are stored respectively in latch circuits 17, 18, 19, the result is inputted again the vector/exponent converting section 2 and outputted to latch circuits 12, 13 as a vector.
申请公布号 JPS60212034(A) 申请公布日期 1985.10.24
申请号 JP19840067547 申请日期 1984.04.06
申请人 NEC HOME ELECTRONICS KK 发明人 ITOI TETSUSHI
分类号 H03M13/00 主分类号 H03M13/00
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