发明名称 MEMORY CIRCUIT
摘要 PURPOSE:To obtain an address multiplex dynamic RAM capable of a high speed action ranging over plural lines by renewing an address for specifying a memory cell group when the address for accessing to a memory cell in memory cell groups reaches the prescribed number. CONSTITUTION:Columns of, for instance, two groups, memory cell groups 12 and 13 are specified by an address of an address register 9, while readout data etc., from the groups 12 and 13 are outputted by means of access through row address registers 14 and 15 in accordance with a group specifying address such as one bit of a register 10. When the row address is beyond the prescribed number corresponding to the final row, the address of the register 10 is renewed by a row address decoder 11, and an access row is substantially increased by ''1'', etc. This constitution accomplishes an address multiplex dynamic RAM capable of a high speed action ranging over two lines or more.
申请公布号 JPS60211690(A) 申请公布日期 1985.10.24
申请号 JP19840067643 申请日期 1984.04.06
申请人 HITACHI SEISAKUSHO KK 发明人 ACHIHA MASAHIKO;AOKI MASAKAZU;HORIGUCHI SHINJI;ISHIKURA KAZUO
分类号 G11C11/401;G06F12/02;G06F12/06;G11C11/34;(IPC1-7):G11C11/34 主分类号 G11C11/401
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