发明名称 RAM CONTROL CIRCUIT
摘要 PURPOSE:To obtain a control circuit coping with both systems using a RAM and two RAMs by providing a switching circuit of a write enable signal and an output enable signal of the RAM and an exclusive OR circuit for address signal outputs. CONSTITUTION:In a circuit switching the two systems by means of a control signal, when a control signal 81 is at an H level, the system using two RAMs is attained by selecting switching circuits 82-84 as shown in the figure. That is, an output terminal A has a write enable signal WE1, an output terminal B has a WE2, an output terminal C has an output enable signal OE1 and an output terminal D has an output signal OE2. When the level of the control signal 81 is at L level, the system is switched to the system using one RAM by selecting the switching circuits 82-84 in opposite position from Fig., and the output terminal B has a write enable WE, the C has an output enable OE and the D has a signal of exclusive OR between the W/R signal and a RAM switching signal.
申请公布号 JPS60211538(A) 申请公布日期 1985.10.23
申请号 JP19840068800 申请日期 1984.04.05
申请人 MATSUSHITA DENKI SANGYO KK 发明人 KIHARA NOBUYOSHI
分类号 G06F5/10;G06F5/06 主分类号 G06F5/10
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