发明名称
摘要 PURPOSE:To increase the yield of the non-defective unit by deciding the quality of the semiconductor memory through comparison between the defective address number of the meanured memory and the threshold defective address number. CONSTITUTION:The test pattern is produced through microprogram pattern genarator 5, and the address information to be tested is given to X and Y address decoder 3 and 4 plus 9 and 10 of measured memory 1 and fail buffer memory 7. Then the output signal of memory 1 is compared with the exectaion information given from generator 5 through quality decision circuit 6. And the fail identification information is writtern into the address of corresponding memory 7 only when no coincidence is obtained. After the pattern end, the address signal is generated from sequential address counter 11, and memory 7 is read out to count the number of the defective signal through defective number counter 12. After this, the threshold defective address number set in register 14 is compared with the count number of counter 12 through count comparator 13. Based on the result, the quality is decided for memory 1.
申请公布号 JPS6047679(B2) 申请公布日期 1985.10.23
申请号 JP19770114847 申请日期 1977.09.22
申请人 NIPPON ELECTRIC CO 发明人 NIGORIKAWA ATSUSHI;MATSUOKA OSAMU
分类号 G11C11/413;G01R31/28;G06F11/34;G11C29/00;G11C29/44 主分类号 G11C11/413
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