| 摘要 |
PURPOSE:To contrive the increase in capacitance per unit area by a method wherein a P type Si substrate immediately under the electrode of an MOS capacitor is provided with the first N-layer, a P-layer connected to the substrate, and the second N-layer continuous to the first N-layer. CONSTITUTION:After the N-layers 9 and 12 are formed in a P type Si substrate 1 by the same diffusion, the P-layer 10 is provided selectively at the intermediate section by ion implantation. Therefore, a capacitor made by P-N junction is formed in the substrate in addition to the MOS capacitor on the surface, and the amount of charge accumulation increases. For example, when the oxide film under the capacitor electrode 5 is 250Angstrom , the MOS capacitance value is 4.14X10<-7>F/ cm<2>, whereas the P-N junction capacitance value is corresponding to about 2X 10<17>F/cm<2> when the concentration of the substrate 1 is 4X10<17>/cm<2>, resulting in the number of the P-N junction planes by two; therefore, this value becomes about twice of the case of utilizing only the surface. Accordingly, the integration can be increased by reducing the element dimension in order to obtain the same capacitance value. |
