发明名称 MEMORY INTERFACE CIRCUIT
摘要 PURPOSE:To connect plural kinds of RAMs or ROMs to a composite function CPU through the mode designation by providing a memory address signal generating means, expansion register and a selector for various modes. CONSTITUTION:Memory address signal generating means 91-94 have similar functions of an interface circuit in case of the constitution of memory for modes 0-3 respectively. Further, an expansion register 95 is set by the software and an S-RAM8K byte mode signal SR8K is outputted. A selector 96 inputs the signal SR8K, a memory mode select ''0'' signal MMSO and memory mode select 1 signal MMS1, one of outputs of means 91-94 is selected and designated and outputted as the memory interface circuit 77. That is, the signal MMSO, the signals MMS1 and SR8K are brought into high or low level to select and designate the mode thereby connecting the plural kinds of RAMs or ROMs to the composite function CPU.
申请公布号 JPS60211555(A) 申请公布日期 1985.10.23
申请号 JP19840068273 申请日期 1984.04.04
申请人 ASUKII:KK 发明人 ISHII TAKATOSHI;YAMASHITA RIYOUZOU
分类号 G06F12/06 主分类号 G06F12/06
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