| 摘要 |
<p>A digital video signal processing circuit generates non-interlaced lines of video information ("progressive scan") from interlaced composite color video signal including a luminance signal which contains vertical detail inform- tion without peaking. There are two progressive scan speed-up processors (PSP1,PSP2) functioning in parallel and controlled to operate alternately, the one in a reading mode and the other in a writing mode, and vice versa. Each receives the interlaced luminance and chrominance signals. In each of the speed-up processors, a line of chrominance signals (I,Q) is time compressed and repeated to generate two lines (1" 2x, I" 2x or Q" 2x, Q" 2x) of time compressed chrominance video for each line of interlaced chrominance video (Figure 3j,k). Furthermore, in each of the speed-up processors, a vertical detail signal (Y" D) is regenerated that contains vertical detail information derived from the interlaced luminance signal (Y). The vertical detail signal is nonlinearly processed (57) to generate a vertical peaking signal (Y" P) that is combined (58) with the vertical detail signal. A time compression stage (60b) speeds up the peaked vertical detail signal (Y; + YP) to a double line rate (Y" 2xV). Another time compression stage (60c) speeds up a luminance signal (Y" cm) containing high frequency information. The time compressed peaked vertical detail signal and the time compressed high frequency luminance signal are combined (59, MUX2,62,61) to generate a time compressed enhanced luminance signal, such that alternate lines (Y" 2x-,Y" 2x+) of the enhanced luminance signal contain vertical peaking information of opposing polarities. The outputs of the two speed-up processors are multiplexed (MUX1, FIG1) and applied to a color matrix (37) to generate the time compressed lines of noninterlaced red, green and blue signals.</p> |
