| 摘要 |
PURPOSE:To reduce the frequency in main storage reference of the same data by providing a scalar register where data, which has the just preceding element number and is stored in the 0th element part of a vector register. CONSTITUTION:A series of data A2-A(N+1) taken out from a main storage 1 are written in vector registers 10 and 12 by a main storage reference control circuit 2. Contents of the vector register 10 and a scalar register 20 where data A1 is preliminarily written in the preprocessing of the processing of a vector instruction are read out, and a result VRi is written in a vector register 11, and data A(N+1) is written in the scalar register 20 by the processing to SR. The subtraction result of every element between A1-AN of the vector register 11 and A2-A(N+1) obtained in the vector register 12 is written in a vector register 13. |
