发明名称 GENERATION SYSTEM OF PARALLEL PROCESSING INSTRUCTION
摘要 PURPOSE:To shorten an execution time by generating an instruction which gives execution conditions in case that divided instruction groups to be processed in serial are processed in parallel. CONSTITUTION:With respect to instructions 1-7 to be processed in series in numerical order, instructions 1-3, the instruction 4, and instructions 5-7 are assigned to three processors respectively by assigning instructions 9-11, and the execution order of instructions 1-7 is controlled by an inter-instruction order instruction 12, and, for example, the instruction 7 is executed after execution of the instruction in the different processor. Thus, the execution time is reduced to 3/7 in this example.
申请公布号 JPS60209843(A) 申请公布日期 1985.10.22
申请号 JP19840065719 申请日期 1984.04.04
申请人 HITACHI SEISAKUSHO KK 发明人 TSUKIZOE AKIRA
分类号 G06F9/38;G06F9/44;G06F15/16 主分类号 G06F9/38
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