| 摘要 |
PURPOSE:To attain the more efficient and effective use of a fail memory and to attain the efficiency improvement and economization of a memory test, by using a fail memory of a complete set to bracket when necessary a multiple and simultaneous test of high-speed memories, large-capacity memories of low-speed memories. CONSTITUTION:A memory part 50 consists of four memory blocks 51-54, for example, corresponding to input channels C1-C4 respectively. These input write signals W are applied from a test result input part 10 in the form of pulse signals when the test result is not satisfactory. While an address A of a defective area is supplied to the blocks 51-54 respectively from an address input part 40. In this test method, the constitution can be rearranged into a serial/parallel structure for memory blocks of a fail memory in accordance with the capacity of a memory to be tested and the number of channels and the speed of a multiple and simultaneous test. Thus it is possible to perform tests of various high- speed and large-capacity memories in each or a multiple and simultaneous test of a high-speed interleave fetching mode, a parallel mode for fetching multiple units and a fetching mode of a serial mode for fetching large capacity respectively.
|
