| 摘要 |
PURPOSE:To prevent the generation of difference in bus using efficiency by varying the sending interval of bus using request signals in a direct memory access transfer control type data processor. CONSTITUTION:When data transfer is normal, a transfer period T is not changed, but when overrun is generated in a channel device 4, an error interruption to a central processor 2 is generated and a transfer period setting command for newly specifying a different transfer period is sent to a channel device 4 to change the transfer period. Consequently, the channel device 4 sends a request data signal RQDT at a different period. Under control by a central control device 2, the transfer period is expanded such that a common bus can be used by respective channels when the common bus is confused. When the common bus is idle, the transfer period is shortened so as to end rapidly the specified transfer. |
