发明名称 MANUFACTURE OF COMPLEMENTARY TYPE MOS INTEGRATED CIRCUIT
摘要 PURPOSE:To manufacture an integrated circuit in CMOS-SITs operating at high speed and low power consumption by implanting the ions of boron or phosphorus to each of drain and source regions in a PMOS-SIT and an NMOS-SIT. CONSTITUTION:Boron ions are implanted to a PMOS-SIT region by an Al mask 40 in drain and source regions in the PMOS-SIT region, thus forming P<+> regions 14, 15. Phosphorus or arsenic ions are implanted to an NMOS-SIT region, thus shaping N<+> region 16, 17. Openings are bored to drain and source regions in the NMOS-SIT and the PMOS-SIT through a mask method, and Al layers 22 are vacuum-deposited to said opening regions and an N<+> substrate, thus forming electrodes. Consequently, a CMOS-SIT integrated circuit is shaped. According to the method, the integrated circuit can be manufactured easily, and the integrated circuit, which has excellent low power consumption and operates at high speed, can be obtained.
申请公布号 JPS60207368(A) 申请公布日期 1985.10.18
申请号 JP19840064675 申请日期 1984.03.31
申请人 SHINGIJIYUTSU KAIHATSU JIGIYOUDAN;NISHIZAWA JIYUNICHI;SUZUKI SOUBEI 发明人 NISHIZAWA JIYUNICHI;SUZUKI SOUBEI
分类号 H01L27/08;H01L21/336;H01L21/8238;H01L27/092;H01L29/78 主分类号 H01L27/08
代理机构 代理人
主权项
地址