发明名称 DECIMAL MULTIPLIER
摘要 PURPOSE:To reduce the number of arithmetic steps and to perform processings at a high speed by adding a specific circuit for arithmetic control to a multiplying circuit for addition/subtraction processings of numerical data. CONSTITUTION:Before the adding arithmetic of a multiplicand is started, high- order one digit (partial multiplier) of a register 111 is selected by a selector 113 and is stored in a register 114, and simultaneously, it is checked by a detecting circuit 117 whether the partial multiplier is ''1'' or not, and a flip flop 119 is set to ''1'' if the partial multiplier is ''1''. If the partial multiplier is not ''1'', the partial multiplier is used as an input A of an adder 116, and ''-1'' selected by a selector 115 is used as input B of the adder 116, and ''-1'' is added to the partial multiplier by the adder 116 simultaneously with the adding arithmetic of the multiplicand in the adder 116, and ''1'' is subtracted from the partial multiplier. This subtraction result is selected by the selector and is stored in the register 114, and simultaneously, it is checked by the detecting circuit 117 whether the result is ''1'' or not, and hereafter, the similar operation is repeated.
申请公布号 JPS60205747(A) 申请公布日期 1985.10.17
申请号 JP19840062759 申请日期 1984.03.30
申请人 TOSHIBA KK 发明人 TASHIRO SHIYOUJI
分类号 G06F7/496;G06F7/491;G06F7/52;G06F7/527 主分类号 G06F7/496
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