| 摘要 |
<p>PURPOSE:To reduce the circuit scale with a signal converter by using a means which performs the M-degree descrete Fourier transform to a circuit which performs the cyclic convolution for chirp Z conversion. CONSTITUTION:A circuit 43 which performs the cycle convolutional calculation is provided with a circuit 11 which performs the prescribed matrix calculation, delay circuits 21-23 and adders 24 and 25. The circuit 11 consists of coder inverter 26, an M-degree adverse DFT circuit 27 and a fixed coefficient multiplier 28. Then an adverse FFT (fast Fourier) circuit ie available in place of the circuit 27 in case M is equal to an exponent of '2'.</p> |
