发明名称 Memory control apparatus for a CRT controller.
摘要 <p>A memory control apparatus for a CRT controller is dis- dosed. When the same data from a data input circuit (123) is loaded into a plurality of addresses of a buffer memory (100) for storing drawing data, the address of the buffer memory (100) is automatically updated. X- and Y-address generators (106, 107) update address data in response to pulses from X- and Y-axis pulse generators (108, 109). A microprocessor supplies to register (114, 117) the width of the X and Y thickness of an address to be updated, and coordinate data representing a write start point to the address generators (106, 107), and the drawing data to be written to a data input circuit (123).</p>
申请公布号 EP0158209(A2) 申请公布日期 1985.10.16
申请号 EP19850103530 申请日期 1985.03.25
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 TAKASHIMA, SHIGEKAZU C/O PATENT DIVISION;SAKAMOTO, TSUTOMU C/O PATENT DIVISION
分类号 G09G5/393;(IPC1-7):G09G1/16 主分类号 G09G5/393
代理机构 代理人
主权项
地址