| 摘要 |
PURPOSE:To prevent the reduction of a transmission efficiency by writing a first half of a data relayed in advance to an FI, FO buffer memory before a relayed data is inputted so as to reduce the delay in the time caused by relay. CONSTITUTION:A data (a) is inputted to a reception circuit 11 of a data relay system at a time t1 so as to output a reception enable signal (b), a reception data (c) and a reception clock (d) respectively for a prescribed time. The data (c) and the clock (d) are ORed with a pre-write clock (n) and a pre-write data (p) of a reset pre-write circuit 16 at OR gates 12, 13 and the 1st half of the data relayed in advance is written in the FI, FO buffer memory 14. Then the signal (b) is fed to a synchronizing circuit 15, an OR gate 18, the circuit 16 and an AND gate 17 apply reading processing, the delay of data transfer to the transmission circuit 19 is prevented so as to improve the transmission efficiency of data. |
