| 摘要 |
A system and procedure for organizing a digital memory by incorporating error correcting circuitry and error detecting circuitry into the memory based on the graph of an error-correcting code in tree form. The error detecting circuitry detects a variety of multiple errors in stored binary bits, and in addition detects certain failures in the memory circuitry. One embodiment coordinates a series of independent memory subarrays in an interdependent manner so that all of the bits in an arbitrarily large memory are organized so as to form several long code words in a single-error-correcting double-error-detecting code. Another embodiment organizes all of the bits in the memory so that they form a single codeword in a double-error-correcting, triple-error-detecting code derived from a projective plane. Coding efficiency is high: in the cases of a 256K memory, including the required parity check bits, only (33/32) 256K bits, approximately, must be stored. Single error correction can take place at the time of a read with very little additional delay compared to that of a normal irredundant memory.
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