发明名称 |
Self-aligned manufacture of FET |
摘要 |
This specification discloses a self-aligned manufacturing method of a Schottky gate FET. This method comprises the steps: forming a gate metallic layer on a semiconductor substrate and a mask overhanged on the metallic layer; ion-implanting impurity ions into the semiconductor substrate using the mask to form a source/drain region; depositing an insulator on the gate metallic layer side surface and the other surface below the mask; directionally etching said deposited insulator using the mask to expose the source/drain region; depositing a source/drain electrode using the mask; and removing the mask.
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申请公布号 |
US4546540(A) |
申请公布日期 |
1985.10.15 |
申请号 |
US19830531709 |
申请日期 |
1983.09.13 |
申请人 |
HITACHI, LTD. |
发明人 |
UEYANAGI, KIICHI;UMEMOTO, YASUNARI;TAKAHASHI, SUSUMU;NAKAMURA, MICHIHARU |
分类号 |
H01L21/265;H01L21/311;H01L21/338;H01L29/417;H01L29/80;H01L29/812;(IPC1-7):H01L29/48;H01L21/308 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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