| 摘要 |
PURPOSE:To attain a RAM writing system which can increase the data writing speed to plural RAM chips by providing a means which selects those RAM chips as the same time and ensuring a memory access with high efficiency. CONSTITUTION:When a CPU1 delivers B''01000'' to AD11-AD15, the output of an NOR gate 6 is set at ''1''. Then chip selection lines CS0'-CS7' are all set at ''1'' by an OR gate 7 regardless of outputs CS0-CS7 of a DEC3. Thus RAM0-RAM7 are selected at a time. Therefore it is just required for the CPU1 to change AD0-AD15 to X''4000''-X''47FF'' in order to give accesses to all words of RAM0-RAM7. In this case, the word writing frequency is set at 2,048 and the writing is possible for all RAM chips 2. Furthermore no effect is given to an individual access of each chip 2 since the address data on a free area 8 is used. |
