发明名称 DATA PROCESSING SYSTEM
摘要 PURPOSE:To facilitate a self-clock by performing coding and decoding after securing the correspondence between the 8-bit data and a prescribed 17-bit code. CONSTITUTION:A prescribed 17-bit code is stored in an address 255 from an address 0 of a ROM102. When the data series are supplied to a shift register 100 from an input terminal (a), an address corresponding to the data is designated with the ROM102. Then the stored 17-bit code is read out to the designated address and then supplied to a shift register 103 to be delivered through a code output terminal (b). Thus adverse conversion is carried out in a decoding mode after the coding is through. As a result, the minimum reverse interval is set at 1.41T together with the maximum reverse interval and the detection window width set at 5.18T and 0.47T respectively (T: data bit interval). This facilitates a self-clock.
申请公布号 JPS60203023(A) 申请公布日期 1985.10.14
申请号 JP19840059198 申请日期 1984.03.27
申请人 CANON KK 发明人 TOKUUME YOSHIHIRO;TSUJII SHIGEO;KUROSAWA KAORU
分类号 H03M5/14;H03M7/14;(IPC1-7):H03M7/14 主分类号 H03M5/14
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