发明名称 CCD DELAY CIRCUIT
摘要 PURPOSE:To synthesize the outputs of two CCD delay circuits which are driven alternately with no distortion by connecting the collectors of two differential circuits in an X shape and controlling the current sources of both differential circuits with outputs of both delay circuits. CONSTITUTION:Both CCD delay circuits 12A and 12B are connected in parallel in order to attain a sampling speed higher than the working limit level of CCD. Then both circuits 12A and 12B are driven alternately by clocks CK and the inverse of CK to attain apparently a double sampling speed. The outputs of both delay circuits are synthesized by switching a switch circuit 19 with both clocks CK and the inverse of CK. The circuit 19 consists of two differential circuits (30, 31, 41) and (32, 33, 44) with collectors connected in an X shape. Both differential circuits are driven alternately with clocks and therefore the outputs of both CCD delay circuits supplied to terminals 42 and 45 are synthesized and delivered to an output terminal 40.
申请公布号 JPS60201715(A) 申请公布日期 1985.10.12
申请号 JP19840057999 申请日期 1984.03.26
申请人 SONY KK 发明人 MOTOYAMA TADASHI;HIYOUDOU KENJI
分类号 H03H11/26;(IPC1-7):H03H11/26 主分类号 H03H11/26
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