发明名称 REJECTION SIGNAL MEMORY CIRCUIT FOR SELECTION REJECTER
摘要 PURPOSE:To make modulation work ever so easy, by installing a memory circuit capable of modulating the memory time of a rejection signal through modulation for oscillating frequency in an oscillation circuit, in a device which rejects a defective article with a rejector by means of the rejection signal out of a checker judging the defective article. CONSTITUTION:A distance of a rejecting position II rejecting a defective article from a check position I checking its quality is set down to L and maximum dimensions corresponding to a conveying direction of the article to D, respectively, n progress counters 11-14 of the specified number being larger than these L and values are installed. Likewise, a symmetrization circuit 15, which symmetrizes each rejection signal (a) out of a checker and inputs it into each of these counters 11-14 as count starting signals (b)-(e), is installed. And, clock pulses out of an oscillation circuit 16 capable of modulating oscillating frequency are inputted into each clock pulse input terminal of these counters 11-14, and when a signal (g) is outputted from any of these counters 11-14, a rejecter 2 is constituted so as to be operated via a gate circuit G2.
申请公布号 JPS60202015(A) 申请公布日期 1985.10.12
申请号 JP19840055986 申请日期 1984.03.26
申请人 HITACHI MEDEIKO:KK 发明人 SHIMIZU HIROSHI;MIYATAKE SHIYOUZOU
分类号 B65G43/08;B07C5/36;B65B57/00;B65B57/10;B65G47/51 主分类号 B65G43/08
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