发明名称 DELAY CIRCUIT OF CARRIER CHROMINANCE SIGNAL
摘要 PURPOSE:To constitute inexpensively a circuit and to improve a frequency characteristic by selecting a clock frequency of a charge transfer element to the prescribed frequency less than twice the upper limit frequency of a carrier chrominance signal. CONSTITUTION:A standard type-coler video signal incoming to an input terminal 1 is supplied to a band filter 2, where only a carrier chrominance signal is separated and extracted, and supplid to a sampler 3. Lower and upper limit frequencies of an input carrier chrominance signal are asumed to be f1 and f2, respectively. A frequency spectrum of an output signal of the sampler 3 obtained when a sampling frequency fs is selected as 2f1, becomes the state as shown in the figure (C), while the spectrum obtained when the sampling frequency fs is selected as below 2f1 (<2f1) becomes the state as shown in the figure (D). Thus the mumber of bits of a CD5 can be constituted in 1,006 or less bits and can be further minimized as compared with 1,262 bits of a conventional case, whereby a delay circuit can be inexpensively made.
申请公布号 JPS60200693(A) 申请公布日期 1985.10.11
申请号 JP19840057093 申请日期 1984.03.24
申请人 NIPPON VICTOR KK 发明人 NAGAOKA YOSHINORI;SHIBAYAMA TAKECHIKA
分类号 H03H11/26;H04N9/64;H04N9/84 主分类号 H03H11/26
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