| 摘要 |
PURPOSE:To make chip area small by not making the correction of one output out of data bit outputs. CONSTITUTION:A memory 13 for parity check and a parity output section 14 consists of for two bits, and an error detecting circuit 15 consists of two threeinput gate circuits G-11,G-12 and three two-input AND circuits AND-11-AND-13. Both of gate circuits G-11,G-12 that make output X=ABC+A(-B)(-C)+(-A)B(-C)+(-A)(-B)C, and ''1'' is outputted when there are odd number of ''1'' in input, and ''0'' is outputted when there are even number of ''1''. An error correcting circuit 16 consists of three exclusive OR circuits, and data of the memory 13 for parity check are made ''0'' to make the output of the gate circuit G-11 ''0'' as the data bit output is ''0'', ''0''. |
