| 摘要 |
PURPOSE:To release a processor bus except the time of starting and completion of transfer between memories by making data transfer between memories through a direct memory access controlling circuit. CONSTITUTION:When a CPU transfers data from a memory MM1 to a memoru MM2 to the direct memory access controlling circuit for data transfer DMAC, start setting is made from the CPU to the DMAC through the processor bus P-BUS. When the condition for starting is made complete, the DMAC reads data from the MM1 through a data bus D-BUS, and similarly, writes data in the MM2. When the transfer of designated quantity of data is completed, the DMAC sends report of completion of memory transfer to the CPU through the P-BUS, and stands by. The CPU attains memory access and I/O control etc. exept when starting and completion. |
