| 摘要 |
<p>PURPOSE:To detect a code error by simple constitution by controlling a sequence of parallel codes from a series/parallel converting circuit by an erroneous pulse t outputted from a comparing circuit of the receiving side, in a detecting circuit for detecting a code error of, especially, one sequence data. CONSTITUTION:In the transmitting side, a parallel code having an (n) bit delay difference is converted to a series code by a clock generating circuit 21, parallel/ series converting circuit 3 and a pseudo random code generating circuit 20; and s sent out from a terminal 6 and 16 together with a clock. In the receiving side, it is converted to a series code inputted by a series/parallel converting circuit 4. In such a case, a clock inputted to a terminal 17 and a clock frequency-divided to 1/2 by a 1/2 frequency divider 11 are used. As for this parallel code, a delay difference generated in the transmitting side by an (n) bit delaying circuit 2 is compensated, and it is inputted to a comparing circuit 12. In case the parallel code does not coincide with the transmitting side, an erroneous pulse is outputted from the comparing circuit 12, and only when many erroneous pulses exist, an output sequence control means 23 is operated, by which the phase of an output of the 1/2 frequency-divider 11 is changed, and the phase of the parallel code from the circuit 4 coincides with the transmitting side.</p> |
