发明名称 MEMORY ACCESS CONTROLLING SYSTEM
摘要 PURPOSE:To improve the quantity of processed data of a memory by providing a device that accesses plural required banks simultaneously as far as the banks are usable. CONSTITUTION:When a start controlling circuit 40 judges that a required bank is not in used by counters 48a-48n, sends out address and a controlling signal. If it is write access, the start controlling circuit 40 takes out the first write data of access waiting stack 46, and sends out to a data transfer line 35. In the case of read access, the start controlling circuit 40 determines plural banks that need access, and decides whether all of these banks are not in use by counters 48a-48n, and if there are banks being used, starts vaceant bank one by according specified order. When all banks are not in use, the circuit sends out address to a transfer line 33, and when a start signal is sent out by a controlling line 31, this address signal is sent to all controlling lines for required banks out of controlling lines 31.
申请公布号 JPS60201453(A) 申请公布日期 1985.10.11
申请号 JP19840057612 申请日期 1984.03.26
申请人 FUJITSU KK 发明人 ITOU SHIYOUHEI
分类号 G06F12/06;(IPC1-7):G06F12/06 主分类号 G06F12/06
代理机构 代理人
主权项
地址