| 摘要 |
<p>Aphasesynchronizationcircuitforcontrollingagraphic display device in a teletext receiving system. The phase synchronization circuit (3) includes a delay circuit (31), adapted to delay in sequence clock signals which are to be phase-synchronized with a reference signal (VSYNC, MSYNC) and to produce in sequence delayed clock signals (K1, K2, ..., Kn) and a selection circuit (32), including set/reset circuits and gates, each gate receiving the output of the set/reset circuits and of the delayed clock signals. Among the delay clock signals, the signal that has the nearest edge timing to the edge of external signals is selected. The phase synchronization circuit has a short pull-in time and high-speed synchronization, is suitable for circuit integration, and offers improved reliability.</p> |
