| 摘要 |
PURPOSE:To avoid unpleasant pattern even when the number of profile correcting signals per vertical synchronizing period is comparatively large by providing a count means receiving the profile correction signals and counting them, a clip means clipping the center of the profile correcting signal in response to the count output and a synthesis means synthesizing an output of the clip means into a video signal. CONSTITUTION:A clip width variable clip circuit 9 has an input terminal 8a connected to a profile correction signal generating circuit 6, an output terminal 8b connected to an adder circuit 3 and a control terminal 8c. An output V1 of a D/N converter 16 is shown in Fig. H. The output V1 responds to a reset pulse P3 shown in Fig. E and becomes zero and reset. Further, an output V2 of a sample-and-hold circuit 18 is shown in Fig. I. Moreover, an output signal E2 of the clip width variable clip circuit 9 is shown in Fig. J. The signal E2 in Fig. J is synthesized with an original video signal S1 at the adder circuit 3 and a video signal S2 subject to profile correction as shown in Fig. K is outputted.
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