| 摘要 |
<p>PURPOSE:To improve the performance of code identification by applying plural code samplings to a bit to be identified and using several points of code samples to identify the bit thereby decreasing the code identification. CONSTITUTION:A code data to be identified from a terminal T10 is given to a limiter 1, fed to a latch circuit 6 and a PLL circuit 11, and an output signal is latched to the circuit 6 by using an n-times clock pulse 202 in synchronizing with the limit output of a VCO113 of the circuit 11. The output 204 being the ANDed (12) output between the output of the circuit 6 and a pulse 202 is fed to an (n+1) notation count 13, and a 1/n-pulse generated from a pulse generating circuit 14 is fed to a reset terminal. Further, a 3-bit data 207 outputted from the counter 13 is latched to a latch circuit 15 by an output pulse 208 of the circuit 14 and a latch data 209 is fed to a majority decision circuit 16. The circuit 16 uses a tail ridge pulse 210 of a unit identification code outputted from the circuit 14 as a latch pulse and outputs a code identification result 211 of the MSB to an output terminal 20.</p> |
