发明名称 |
PROCESSOR INPUT AND OUTPUT SYSTEM |
摘要 |
<p>PURPOSE:To indicate the input/output of data with a hard constitution by using the input and output timing controls and an output period timing means to control the input or output timing of data to a processor. CONSTITUTION:An input cycle counter 1 decides a period of time during which data are supplied after detecting a synchronizing clock. Then a period of time during which data are delivered after the synchronizing clock is detected is decided by an output cycle counter 5. Furthermore an output period counter 6 decides a period during which the data delivered from a processor is delivered onto an external data bus B.</p> |
申请公布号 |
JPS60198668(A) |
申请公布日期 |
1985.10.08 |
申请号 |
JP19840054834 |
申请日期 |
1984.03.22 |
申请人 |
FUJITSU KK |
发明人 |
KOSHIKAWA MASAMI;UMIGAMI SHIGEYUKI |
分类号 |
G06F15/16;G06F13/42;G06F15/177 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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