| 摘要 |
<p>PURPOSE:To reduce the power consumption of a dynamic logical circuit by producing an internal clock signal with a supplied external clock signal and delivering said internal clock signal and an output signal obtained by dividing said clock after switching both signals through a switch circuit. CONSTITUTION:An external clock signal 1 supplied from an external clock is converted into an internal clock signal 2 through an internal clock generating circuit A. This signal 2 is divided by a dividing circuit D to obtain a divided clock signal 5. Both clock signals 2 and 5 are supplied to a switch circuit E, and a selected signal 6 is delivered to an internal dynamic circuit B. The circuit B selects and supplies the signal 2 in its normal working mode and then the signal 5 in other modes. Thus the power consumption can be reduced in an execution mode with the signal 5 compared with the normal working mode.</p> |
