INTEGRATED CIRCUIT INCORPORATING PROCESSOR AND MEMORY

摘要

PURPOSE:To simplify the interface conditions to an LSI by providing a processor which can supply an access to a memory from outside. CONSTITUTION:A CPU block 2 contains an address transmission circuit 201 which sends an address to an address bus 41, a data reception circuit 200 which receives data from a data bus 42 and a data transmission circuit 200 which transmits data to the bus 42. The block 2 also transmits an access control signal to a control signal producing circuit 5 for an external device which is connected to a memory block 3 as well as to external terminals 91 and 92. The block 3 contains an address reception circuit 301 which receives an address from the bus 41, a data reception circuit 300 which receives data from the bus 42 and a data transmission circuit 302 which transmits data to the bus 42. The read and write accesses of the block 3 are controlled with a memory block control signal produced from the circuit 5. This LSI1 has a function which performs data input/output between the block 3 and an external bus of the LSI1 under the control of the block 2.