| 摘要 |
PURPOSE:To detect a memory circuit generating an error for a short period by forming a parity generating circuit in each memory circuit and adding a parity check bit to data having an error correcting code to store the data. CONSTITUTION:Upper (m+n) bits of writing data from a data bus 1 are stored in a general register 6-1 as data information 3 together with an error correcting code 5 generated from an error correcting code generating circuit 4. The parity generating circuit 8-1 forms a writing data parity 9-1 on the basis of the data stored in the register 6-1 and stores the formed data in a memory circuit 20-1 together with writing data 7-1 in each memory. At the reading of data from the memory circuit 20-1, a parity check circuit 12-1 checks the parity, and if an error is generated, generates error information 13-1 to inform the generation of an error in the memory circuit 20-1 to the external. |
