| 摘要 |
PURPOSE:To improve the processing speed and processing efficiency of a CPU, by providing a memory for direct memory access in an I/O channel board and directly performing memory access transfer without passing through a system bus. CONSTITUTION:In an I/O channel board 8, a RAM13 is provided instead of a bus controlling system and the RAM13 is controlled by a direct memory access controller (DMAC)10. Namely, the DMAC10 controls the data transfer between an I/O controlling circuit 9 and the RAM13. The DMAC10 accesses the RAM13 inside the board 8 without using a system bus 4. Therefore, the necessity of a bus controlling circuit in the I/O channel board 8 is eliminated. In addition, the bus 4 utilizing efficiency of the CPU2 is improved since the DMAC10 does not require the bus 4 for accessing a RAM7. On the other hand, the RAM13 can be accessed from th other through the bus 4, the CPU2 can easily access data in the RAM13. |
