| 摘要 |
PURPOSE:To detect more precisely the malfunction of a microprocessor, by previously setting odd and even parties in the instruction code of the microprocessor and performing parity checks at every instruction fetch. CONSTITUTION:Instructions outputted from a microprocessor MPU are inputted in a parity generator GEN at every instruction fetch and subjected to parity checks. When an instruction is rejected by the parity check, a high voltage is outputted to an FF circuit JK and a synchronizing signal SYNC outputted from the microprocessor MPU synchronously to every fetch and a clock CLK are inputted in an AND gate G. Then the FF circuit JK is set by the AND signal of both the signal SYNC and clock CLK and an alarm signal ALM is transmitted. Simultaneously, the processor MPU is reset by driving a reset circuit RESET. Moreover, the FF circuit JK is also reset to keep ready for the next error occurrence. |
