| 摘要 |
PURPOSE:To reduce a plane occupying area and to microminiaturize an element formed on a semiconductor substrate by constructing the elemenet of a vertical FET, and burying the FETs and wirings in an insulator. CONSTITUTION:An N<+> type source region layer 2, a P type gate region layer 3, and an N<+> type drain region layer 4 are laminated and formed in a main surface of a P type silicon substrate 1. A gate insulating film S of an SiO2 is formed adjacent to the layer 3, a gate electrode 6 made of polycrystalline silicon is formed to construct MOSFETs QA, QB, QC and QA', QB', QC'. The MOSFETs are surrounded by an insulator layer 7 which mainly contain SiO2, and wirings 6a formed integrally with a gate electrode 6 are buried in the substrate 1 in the state surrounded by the layer 7. The gate length of the MOSFET and the size such as the width of the source and drain region are generated in the thickness wise direction of the substrate 1, thereby extremely reducing the occupying area. |
