| 摘要 |
PURPOSE:To lessen the parasitic resistance, the parasitic capacity and the parasitic inductance by a method wherein the gate electrode is formed on a channel alone and is formed in a form that part of the gate electrode is in contact with the source region and an oxide film provided on the source electrode. CONSTITUTION:A metal gate electrode 8 is provided in a form existing on a channel alone, and at the same time, is provided in a form that part of the metal gate electrode 8 is in contact to the sidewall part of an oxide film 7 provided on a source region 1 through an N type high-impurity concentration polycrystalline Si region 2, which works as a part of a source electrode as well. Therefore, the crosssectional area of the electrode 8 can be made larger in spite of facts that there exists little overlap part of the electrode 8 and the region 1 and there exists little overlap part of the electrode 8 and a region 3. As a result, it is possible to reduce the parasitic capacity, parasitic resistance and parasitic inductance. Moreover, the region 1 has been directly connected electrically to a chip substrate 6 through an auxiliary metal electrode 11, and at the same time, a P type back gate region 5 is also in contact directly to the substrate 6. Accordingly, it is made possible to directly fix the element on a metal header at the mounting time of the element. As a result, a reduction of thermal resistance and grounding inductance is realized. |
