| 摘要 |
PURPOSE:To smooth the acquisition of synchronism of a PLL by allowing the PLL of a data speed converting section to hold the phase before switching for a prescribed period when the active radio line is changed over to a spare line. CONSTITUTION:A write CLK1 of an elastic memory 21 is formed by a 1/n frequency division counter CT 23 from an input clock CLK in the data speed converting section at the transmission end of radio lines comprising active and spare lines and the CLK1 is inputted to a PLL 25 via a changeover switch SW24. An output CLK' of the PLL 25 is inputted to a 1/m frequency division CT27, from which an inhibition pulse is formed, and a read CLK2 of a selector 22 is formed from a 1/n frequency division CT 29 through the combination of the CCK', and the result is inputted to the PLL 25. The PLL 25 is operated to synchronize the phase of the CLK1 and CLK2. If the active line is faulty and a switch signal to the spare line is inputted to a terminal 30, an SW 24 is connected to the upper position by a time tau, the CLK2 is inputted to both input terminals of the PLL 25 to hold the phase before switching, the CT 23 is reset, the phase of the CLK1 is controlled after the time tau to smooth the acquisition of synchronism of the PLL 25. |
