发明名称 LINE QUALITY SUPERVISORY CIRCUIT
摘要 PURPOSE:To supervise the quality of a line at both terminal stations and also to allow individual intermediate relay station to supervise the quality of the line of one section of the own station and the preceding station by providing a supervisory means based on the supervisory result of the preceding station in addition to the means for supervising data by parity check in this line quality supervisory circuit. CONSTITUTION:Data signals 100-1-100-N received from the preceding station are inputted to input terminals 1-1-1-N in a radio digital transmission. A counter circuit 3 counts a mark signal included in an N-line of signals for a desired section and outputs the result of count as a count signal 101. A check bit extraction circuit 4 extracts the parity check bit included in the data signal 100-1 under the control of a control signal 102 and outputs a parity check signal 103. A comparator circuit 5 compares the count signal 101 and the parity check signal 103 and outputs the result as a comparison signal 104. A fault detection circuit 6 detects the presence of a fault of a line before the own station by using the comparison signal 104 and outputs a fault warning signal 105 when a fault exists.
申请公布号 JPS60192440(A) 申请公布日期 1985.09.30
申请号 JP19840047090 申请日期 1984.03.14
申请人 NIPPON DENKI KK 发明人 NAKAJIMA MASAHIRO;HASHIMOTO HIROMI
分类号 H04L1/00;(IPC1-7):H04L1/00 主分类号 H04L1/00
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