| 摘要 |
PURPOSE:To attain ease of multiplex for data of plural terminal devices by generating a transfer clock corresponding to a transfer speed of each signal based on a clock and a frame signal applied from the line and extracting data sequentially from a buffer memory in response to the said transfer speed. CONSTITUTION:When a fixed bit is detected from data of a data line 219 in a fixed bit detection/addition circuit 220, a clock from a transfer clock line 206 of a line is supplied to a transfer clock line 215 and a part excluding the preceding and succeeding fixed bit out of the data from the data line 219 is written on a buffer memory 209. If the fixed bit representing the youngest number is detected before the n-th buffer memory is not written, the clock from the transfer clock line 206 at the line side is switched immediately to the transfer clock line 215 to write the data on the buffer memory 209. Bits (n-set) are transmitted at the same time by using the clock of a terminal device data clock line 208 asynchronously with writing on the terminal device. |
