| 摘要 |
PURPOSE:To suppress the potential boosting of a low-level complementary output as well as to accelerate the rise time on high level side by a method wherein crossunder resistance is reduced by providing a buried contact using polysilicon, for example, on a crossunder resistance part. CONSTITUTION:Polysilicon 16 and a buried contact hole 17 are provided on the crossunder wiring 15 using the N<+> diffusion layer located between an inner node N3 and a grounding wiring Vss. As a result, the parasitic resistance of the source resistance part on a flip-flop circuit can be reduced to one over several integers using the buried contact of the polysilicon 16. Consequently, the rise of the potential of the complementary output -VOUT on the low level side of the flip-flop circuit can be reduced to one over several integers. At the same time, the rising of output of the complementary output -VOUT on the high level side can be performed at a high speed. |
