发明名称 FAULTY DATA RECEPTION PREVENTING CIRCUIT
摘要 PURPOSE:To improve the operation stability of a slave device by presetting a maximum data length of control information received from a master device, deciding the received control information as error if the information exceeds the said maximum data length and stopping the reception for a prescribed time succeedingly to protect the slave device. CONSTITUTION:Before control information received from the master device is written in a memory MEM, the data length is checked by a control circuit CONT to decide whether the length is longer than the specified maximum data length, and when the length is shorter than the specified maximum data, the data is written as it is in the memory MEM and if the length is longer than the specified maximum data length, a flip-flop circuit FF and a timer circuit TIM are set via a peripheral interface adaptor PIA having the function of a peripheral device control interface and the inhibit function of an inhibit gate G1 is operated and the reception is stopped. Thus, it is possible to prevent supply of faulty data from the master device because of a fault of a transmission line or the like.
申请公布号 JPS60192447(A) 申请公布日期 1985.09.30
申请号 JP19840048818 申请日期 1984.03.14
申请人 FUJITSU KK 发明人 KOUNO HISAO;YAMAMOTO KUNIO
分类号 H04L29/14;H04L13/00;(IPC1-7):H04L13/00 主分类号 H04L29/14
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