| 摘要 |
PURPOSE:To correct the frequency in both leading and lagging directions by subtracting a clock pulse of a frequency division stage of a frequency divider and adding the clock pulse to other frequency division output. CONSTITUTION:The frequency divider 2 frequency-divides sequentially the output of an oscillator 1. A clock pulse subtractor 3 subtract a clock pulse of a frequency division stage in the frequency divider 2 at a prescribed rate based on the timing of a timing setting section 4. Further, a clock pulse adder 5 adds the clock pulse variably the frequency division stage of the frequency divider 2 within the summing time adjusted by a control section 6. When the rate of the addition is larger than the rate of subtraction, the frequency is adjusted in the leading direction and when small, the frequency is adjusted in the lag direction. Thus, the frequency is corrected in both the leading and lagging direction. |
