发明名称 BUS TRANSFER SYSTEM
摘要 PURPOSE:To facilitate an easy exchange of input/output devices by extending the address of the input/output device through a bus controller and converting said address into an individual control signal. CONSTITUTION:A bus controller 2 outputs the data sent from a bidirectional data bus 12 to a bus 31 when data are transferred to an input/output device 21 with an indication of a microprocessor 1. Then the address of the device 21 is extended to an input distributor 61 by means of an address bus 11 and an input control signal 13. An input side individual control signal 41 is supplied to an input buffer 71, and the data is set to the buffer 71. In case the data given from an output buffer 72 is transferred to the processor 1, an output distributor 62 outputs an output individual control signal 51 to the device 21 and the buffer 72 by means of the bus 11 and the signal 14 and with an indication of the processor 1. Then the buffer 72 transfers data to the processor 1 via the controller 2.
申请公布号 JPS60191352(A) 申请公布日期 1985.09.28
申请号 JP19840047482 申请日期 1984.03.12
申请人 NIPPON DENKI KK;NIHON DENKI ENGINEERING KK 发明人 MATSUO SHIGE;HORII YUTAKA;MATSUO TAKEYOSHI
分类号 G06F13/14;G06F13/20;(IPC1-7):G06F13/20 主分类号 G06F13/14
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